It has been the trend to scale down the sizes of memory cells to increase the integration level and thus memory capacity of a DRAM chip. As the size of DRAMs is decreased, the capacity of the capacitor used in the DRAM is correspondingly decreased.
A memory cell of DRAM typically consists of a storage capacitor and an access transistor. With the advent of large-scale integrated DRAM devices, the size of the devices has gotten smaller and smaller such that the available area for a single memory cell has become very small. This causes a reduction in the capacitor's area, resulting in the reduction of the cell's capacitance.
One method for increasing capacitance area involves forming hemispherical grain (HSG) polysilicon on amorphous polysilicon and increasing capacitor height. However, increasing capacitor height requires an increase in the amorphous polysilicon layer which requires an increased deposition time for the amorphous polysilicon layer. An increased deposition time causes crystallization of the amorphous polysilicon. Crystallization of the amorphous polysilicon inhibits silicon migration resulting in poor HSG formation atop the amorphous polysilicon. For amorphous silicon deposition, mono-silane (SiH.sub.4) is the reactant gas most frequently used. Although using di-silane (Si.sub.2 H.sub.6) reduces the deposition time, changing existing equipment required is costly.
Therefore, there is a need for an improved method for manufacturing a stack capacitor that reduces crystallization of the amorphous polysilicon and that can be used with existing equipment.